Moderate growth expected for Taiwan's IC packaging sector in 2013
Central News Agency
2013-02-14 07:39 PM
Taipei, Feb. 14 (CNA) Growth in Taiwan's IC packaging and testing sector in 2013 is likely to lag behind that of other semiconductor sectors in the country, a local think tank forecast recently. The production value of the IC packaging sector will grow by between 5.1 and 5.2 percent this year, according to Ray Yang, a manager at the Industrial Economics and Knowledge Center (IEK) under the Industrial Technology Research Institute. That is less than the 7-8 percent growth forecast for Taiwan's DRAM production value, the 6 percent growth projected for the IC design sector and the 5.5 percent growth expected for the country's contract chip makers, Yang said. IC packaging growth will be limited this year because the momentum for new-phase packaging and testing products has yet to be set in motion, leaving the sector without any strong drivers of higher growth, Yang said. Among those potential growth engines are the 3D TSV and 2.5D processes used to create the 3D packages and ICs that are expected to become mainstream in the semiconductor supply chain in the coming years. IEK researcher Chen Ling-chun wrote in a study that large contract chip makers, such as Taiwan Semiconductor Manufacturing Co., United Microelectronics Corp. and Global Froundries Inc., will focus on developing "front-end" 3D TSV and 2.5D processes in 2013. As the large foundries work on developing integrated 3D TSV processes, IC packagers and testers will work on mastering "middle-end" processes that support the advanced TSV manufacturing process, such as embedded die technologies, Chen said. TSMC and other foundries are gearing up to offer their customers complete front-end, middle-end and back-end (assembly and testing) services, potentially threatening the business of dedicated packaging and testing companies. But sources familiar with the sector did not expect Taiwan's packaging and testing industry to respond by developing their own front-end wafer processing capabilities because of cost concerns, instead focusing on mastering middle-end processes. (By Chung Jung-feng and Elizabeth Hsu)
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